1. Field of the Invention
The present invention relates to a signal output circuit for outputting a signal, and a test apparatus including a signal output circuit. The present invention particularly relates to a signal output circuit for outputting a signal in accordance with a predetermined system timing.
2. Related Art
A typical test apparatus for testing a device under test (DUT) such as a semiconductor circuit includes a signal output circuit for inputting a predetermined signal into the DUT and a judging section for judging whether the DUT is good or bad based on an output signal from the DUT.
FIG. 3 shows a configuration of a typical signal output circuit 300. The signal output circuit 300 includes a pattern generating section 310 and a timing generating section 320. The pattern generating section 310 outputs a data signal in response to a clock signal supplied thereto. The timing generating section 320 outputs the data signal output from the pattern generating section 310 in response to a clock signal supplied thereto, in place of the clock signal supplied to the pattern generating section 310.
The pattern generating section 310 includes a delay element 312 and a plurality of flip-flops 314 in a cascade arrangement. The data signal is sequentially propagated among the flip-flops 314 in response to the clock signal supplied to the flip-flops 314 via the delay element 312. Having the above configuration, the pattern generating section 310 inputs the data signal into the timing generating section 320 at a timing determined by the number of stages of the flip-flops 314.
The timing generating section 320 includes a FIFO 322, a write counter 324, a selecting section 326, a read counter 328, a flip-flop 330 and a logical AND circuit 332. The FIFO 322 sequentially receives the data signal output from the pattern generating section 310 in response to the clock signal supplied to the pattern generating section 310. The flip-flop 330 receives data which is sequentially read from the FIFO 322 in response to a clock signal supplied to the timing generating section 320, and outputs the data.
The write counter 324 controls a valid entry in the FIFO 322 into which next data is to be written, and the read counter 328 and selecting section 326 control a valid entry in the FIFO 322 from which data is to be read. The write counter 324 and read counter 328 vary their values each time the counters 324 and 328 write/read data into/from the FIFO 322, so as to keep track of valid entries in the FIFO 322. The logical AND circuit 332 outputs a logical AND between the output of the flip-flop 330 and the clock signal.
With the above configuration, the timing generating section 320 can output a predetermined data signal in response to the clock signal supplied thereto in place of the clock signal supplied to the pattern generating section 310, without causing meta-stable in the flip-flop 330.
In recent years, test apparatuses with a plurality of signal output circuits have been developed. Such a test apparatus can perform a desired test by using a combination of selected signal output circuits. In this type of test apparatus, it is necessary to synchronize the timings at which the signal output circuits output the signals. In other words, the signal output circuits are required to output the signals in accordance with a predetermined system timing.
However, the typical signal output circuit 300 has difficulties in adjusting the timing of outputting the signal. It is possible to adjust this signal output timing at the pattern generating section 310, by selecting a different one of the flip-flops 314 from which the signal is to be output to the timing generating section 320. When the timing at which the pattern generating section 310 outputs the signal is adjusted in the above manner, however, the timing adjustment only has a limited effect because of the FIFO 322, which is provided to prevent meta-stable.
The typical signal output circuit 300 has a different problem. It is difficult to examine whether the signal output circuit 300 operates in accordance with a predetermined system timing.